Out of Order Processor Model

• Introduction
  • Out Of Order Core Features
  • Processor Contexts
  • PTLsim Machine/Core/Thread Class Hierarchy
  
  
• Out Of Order Core Overview
  • Event Log Ring Buffer
  
  
• Fetch Stage
  • Instruction Fetching and the Basic Block Cache
  • Fetch Queue
  
  
• Frontend and Key Structures
  • Resource Allocation
  • Reorder Buffer Entries
    • ROB States
  • Physical Registers
    • Physical Registers
    • Physical Register File
    • Physical Register States
  • Load Store Queue Entries
    • Register Renaming
    • External State
  • Frontend Stages
  
  
• Scheduling, Dispatch and Issue
  • Clustering and Issue Queue Configuration
  • Cluster Selection
  • Issue Queue Structure and Operation
    • Implementation
    • Other Designs
  • Issue
  
  
• Speculation and Recovery
  • Misspeculation Cases
  • Redispatch
    • Redispatch Process
    • Deadlock Recovery
    • Statistical Counters
  • Annulment
    • Branch Mispredictions
    • Annulment Process
  
  
• Load Issue
  • Address Generation
  • Store Queue Check and Store Dependencies
  • Data Extraction
  • Cache Miss Handling
  
  
• Stores
  • Store to Store Forwarding and Merging
  • Split Phase Stores
    • Load Queue Search (Alias Check)
    • Store Queue Search (Merge Check)
  
  
• Forwarding, Wakeup and Writeback
  • Forwarding and the Clustered Bypass Network
  • Writeback
  
  
• Commitment
  • Introduction
  • Atomicity of x86 instructions
  • Commitment
  • Additional Commit Actions for Full System Use
  • Physical Register Recycling Complications
    • Problem Scenarios
    • Reference Counting
    • Hardware Implementation
  • Pipeline Flushes and Barriers
  
  
• Cache Hierarchy
  • General Configurable Parameters
  • Initiating a Cache Miss
  • Filling a Cache Miss
  • Translation Lookaside Buffers
  
  
• Branch Prediction
  • Introduction
  • Conditional Branch Predictor
  • Branch Target Buffer
  • Return Address Stack