[PTLsim-devel] Issues with multiple OOO-cores

Mon Aug 20 14:37:01 EDT 2007

Hi again,
  during testing and code review I 've found that it is possible to use 
the 'ooocore' with multiplie cores in PTLsim/X.

As far as I can see,  ooocore  treats fences and locked memory accesses (as in 
SWAP for example), as no-ops and ignores any side-effects caused by them. 
This is fine for single-core usage, but can IMHO create trouble in a 
multi-core scenario (which actually exists) if one has a multi-cpu domU and 
uses the ooo model, as the 'instant visibility' consistency model still 
allows shuffling of the loads on a core, which could cause inconsistent reads 
from data written by another core.

This might be one of the reasons for using the smtcore, where those 
instructions actually have the expected effects: fences cause ordering 
constraints on memops and locked memops actually take a lock for the duration 
of the x86 op on the modfied address. But then again uops do contend for 
functional units and cache entries in the smtcore.

Is my understanding correct so far?

Why are the fences and locks left out of the ooocore?
Is there a certain reason, why a full SMP (with 'instant visibility' still 
being acceptable) core has not been employed?
Is anybody working on that and willing to share code effort?

I will need a reasonable SMP model for my evaluation work, which I'm doing for 
my  Masters thesis. If there ain't no such yet, I'll have to build my own. 
Hence I'd be grateful to any pointers and hints regarding pitfalls and 
previous attempts in order to avoid repeating encountered errors.

Thanks again for any helpful input!

Kind regards,
  Stephan Diestelhorst
-- 
Stephan Diestelhorst, AMD Operating System Research Center
stephan.diestelhorst at amd.com, Tel.   (AMD: 8-4903)