[PTLsim-devel] Issues with multiple OOO-cores

Wed Aug 22 17:53:35 EDT 2007

Hi Matt,
  thanks for the detailed reply!

> > Probably a small warning banner and a modification of the tutorial (which
> > uses ooocore in PTLsim/X for the initial walkthrough) would be helpful
> > here?
> >
>
> OK, I'll add that. I can just disable ooocore when running in full system mode
> with more than one VCPU.
>
Either way, some notice would be very nice, thanks!

> > This would mean to get rid of (disable) all SMT stuff, such as
> > fetch-priority calculation etc. and probably some care at the mapping of
> > Xen's VCPUs to cores and the transition between them, which I hoped to
> > avoid by doing the port from smt to ooo.
> >
>
> I think the thread priority logic already gets turned off when only one VCPU
> is enabled. If you comment out "#define ENABLE_SMT" in smtcore.h, it will do
> what you want, without actually removing any code.

I have started hacking already yesterday and now have some working
patch which allows multiple single-threaded SMT cores, see attachment.
I'd be very glad to hear any coments on sanity and such.

Basic idea: Add a corecounter to the model and loop through all the
cores at the appropriate places, instead of just using core[0]. This
is triggered by ENABLE_SMT, if defined, every VCPU will get its own
SMT and if undefined, every VCPU will get its own core with a single
hardware thread.

I've found and fixed some problems on my way through the code:

-using default sizes for the register file, the SMT model (with
multiple hardware threads) doesn't support more than three cores, as
the register file is too small for the architectural registers ->
scale PHYS_REG_FILE_SIZE with the number of threads and adapt
MAX_PHYS_REG_FILE_SIZE accordingly.

-the assertion which should actually catch the above problem
(smtpipe.cpp:220) is actually ignored, some general assertion
treatment would be nice, as in some areas they are enabled and in some
disabled :(

-using the smt model without defining ENABLE_SMT seems to be possible,
also when we have multiple VCPUs! Haven't tried it, but IMHO is a bug.
-> Fixed, as we will create multiple cores with the new patch.

-on large testmachines (mine has 16 GB physmem, 8 cores) PTLsim's
reserved memory of 32 MB is insufficient for some internal data
(supposedly pagetables) -> second patch increases (rather arbitrarily)
to 128 MB, this is actually quite trivial!

-the number of SMT_threads is limited to various numbers:
 4 by MAX_THREADS_PER_CORE
16 by MAX_THREADS_BITS
 However, as far as I can see, none of these values is actually
checked against the number of VCPUs n the domain. This is just an
observation and has not yet been fixed.

I hope that these patches make some sense, I'd be happy to hear
suggestions and comments!

Thanks,
  Stephan

P.S.: More on MESI later!
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