[PTLsim-devel] Prefetching

Mon Jul 2 12:26:30 EDT 2007

> > It should be fairly easy to add back in:
> > CacheHierarchy.initiate_prefetch() does what you want. You could add a
> > new function like
> > ReorderBuffer.issue_prefetch() to start the prefetch based on the
> > physical address generated by any OP_ld_pre uops (the cache level is in
> > uop.cachelevel, for PREFETCHTn). Just make a copy of
> > ReorderBufferEntry.issueload() and remove everything except the address
> > generation logic.

Mhmhm, just started with that, but I'm not too confident about the 
implementation details. In particular, I'm not certain about the following 
fields:
  LoadStoreQueueEntry (LSQE) state.invalid
  state.datavalid
  ReorderBufferEntry::cycles_left
and the treatment of the following:
  changestate(core.rob_cache_miss_list)
  LoadStoreInfo lsi (and the associated fileds)

Probably most of that is not needed, but right now I can't figure out proper 
treatment of them..

> Yes - we do have Intel Core Duo style prefetchers and more for L1, L2 in
> an internal version.

Kanad, would you mind sharing such a prefetcher with us?

Thanks,
  Stephan

-- 
Stephan Diestelhorst, AMD Operating System Research Center
stephan.diestelhorst at amd.com, Tel.   (AMD: 8-4903)