[PTLsim-devel] Prefetching

Tue Jul 3 06:56:22 EDT 2007

> I looked at your patch, and you have the right idea, but most of the code
> in issueprefetch() is not needed (in fact it's harmful, since it messes up
> store-to-load forwarding and will block the ROB).
>
> Your problem is that prefetches do not get assigned an LSQ entry - they're
> more like ALU uops that directly talk to the L2 cache controller.

Thanks for the clarification! I was already speculating on the potentially 
corruptive effects of my rather uneducated patch.

> This is probably what you need:

>

Thanks! I have integrated it, patch is attached. Some modifications to address 
generation had to be made, but I guess those were fairly straightforward.

> Notice that it will make the prefetch into a NOP if the address is invalid
> or the TLB doesn't contain a translation. This is consistent with normal
> x86 processors.

Indeed.

Thanks,
  Stephan

-- 
Stephan Diestelhorst, AMD Operating System Research Center
stephan.diestelhorst at amd.com, Tel.   (AMD: 8-4903)
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