[PTLsim-devel] Internal Loads / Stores (LDP / STP) vs. cache hierarchy

Tue Jul 3 15:02:07 EDT 2007

On Tuesday 03 July 2007 11:37, Stephan Diestelhorst wrote:
> Hi,
>   sorry for bothering the list again, but I was (again) wondering about
> some details inside PTLsim...
>
> I was looking at LDP/STP in order to access hidden state inside the core
> and found that those are actually OP_ld / OP_st with internal set to true.
>
> As far as I can see this only changes the address generation (and some
> statistics), other thing progress just as normal loads/stores would,
> especially concerning cache hits and misses.
>
> Is this observation actually correct? I.e. are accesses to private PTLsim
> data actually processed through the whole cache hierarchy? If so, what is
> the reasoning behind this? Wouldn't it be more appropriate to avoid walking
> the caches here, as this data would usually reside inside the cpu and thus
> does not poison our caches?
>

Yes, you're right - this was an oversight on our part. ldp/stp should hit the 
private microcode scratch space (mostly the Context structure) with 2 cycle 
latency and should not go through the cache.

You could add this to the end of issueload():

  ...

  // Add this part
  if unlikely (internal) {
    cycles_left = LOADLAT;

    if unlikely (config.event_log_enabled) 
core.eventlog.add_load_store(EVENT_LOAD_HIT, this, sfra, addr);

    load_store_second_phase = 1;
    state.datavalid = 1;
    physreg->flags &= ~FLAG_WAIT;
    physreg->complete();
    changestate(thread.rob_issued_list[cluster]);
    lfrqslot = -1;
    forward_cycle = 0;

    return ISSUE_COMPLETED;
  }

#ifdef USE_TLB
...
#endif

  return probecache(...);
}

Similar code could be added to commit() for stp stores.

- Matt

-------------------------------------------------------
 Matt T. Yourst                    yourst at peptidal.com
 Peptidal Research Inc., Co-Founder and Lead Architect
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