[PTLsim-devel] ooo-core simulates translation from CISC to uops?

Mon Oct 1 22:24:17 EDT 2007

On Monday 01 October 2007 21:17, Vicente Marrero González wrote:
> Hi,
> i'm a bit lost, i see that the simulator uses bb-cache & trans-ops for
> avoiding a waste of time in simulation but i dont know if there's
> traslation from CISC to uops and if it's reflected in the time of fetch
> stage or decode stage in stats. I've travelled a bit around the source code
> and i couldn't get an answer.

Maybe I misunderstood your question, but the translation process from x86 CISC 
instructions into uops is very extensively documented everywhere in the 
manual and in the code (that's what decode-*.cpp are for).

For a better explanation, see these parts of the manual:

- Chapter 6 (Decoder Architecture and Basic Block Cache)
- Chapter 17 (Fetch Stage)
- Chapter 18.5 (Frontend Stages)

Notice how you can simulate any number of stages normally occupied by decoder 
logic (typically around 5 stages for most Intel and AMD chips) by just 
adjusting FRONTEND_STAGES.

- Matt

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 Matt T. Yourst                    yourst at peptidal.com
 Peptidal Research Inc., Co-Founder and Lead Architect
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