[PTLsim-devel] Memory consistency

Tue Oct 23 08:30:26 EDT 2007

> Real x86 hardware supports AFAIK Total-Store-Ordering as the basic
> memory model. (Let's skip nc, wc and odd things) I was wondering,
> how that was enforced with SMT. Inuitively, this would not be
> necessary, as the SMT should just multiplex front-end and back-end
> structures and essentially maintains a shared core.
>
> Please note that we don't need any fence to ensure ordering here.
> The underlying consistency model should enforce the mentioned
> guarantess.

Actually it turns out that this feature has just recently been 
announced by AMD (in the current manuals) and Intel still allows load 
reordering. Hence it is safe to assume that code relying on the order 
of loads will use lfences where necessary.

So I need to look at other places.. Kind of klinging to straws at 
while my split core model dies.

Cheers,
  Stephan

-- 
Stephan Diestelhorst, AMD Operating System Research Center
stephan.diestelhorst at amd.com, Tel.   (AMD: 8-4903)

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