[PTLsim-devel] [PATCH] Bug in tlbwalk

Tue Sep 11 11:11:07 EDT 2007

Hi list,
  I just found and fixed a bug in tlbwlak that can cause indefinite stalls of 
the core, leading to an abort by the pipeline-deadlocked watcher.

The problem lies in smtexec.cpp, around line 1639:

  cycles_left = 0;
  changestate(thread.rob_cache_miss_list);

  LoadStoreInfo lsi = 0;
  lsi.threadid = thread.threadid;
  lsi.rob = index();

  SFR dummysfr;
  setzero(dummysfr);
  lfrqslot = core.caches.issueload_slowpath(pteaddr, dummysfr, lsi);
  // No LFRQ or MB slots? Try again on next cycle
  if (lfrqslot < 0) {
    //.. 
    return;
  }

As you can see, the rob is put to the rob_cache_miss_list, before we check for 
MB or LFRQ slots. If there are none left, the rob can't be re-tlbwalk-ed in 
the next cycle, as it is not on the tlbmiss_list anymore.

That means that the rob will stay on cache_miss_list forever, as no caches 
will serve the poor guy, eventually stalling the entire core.

Fix: Simple, put on rob_cache_miss_list *after* having allocated LFRQ / MB 
slots!

Patch attached, Signed-off by <Stephan.Diestehorst at amd.com>

Cheers,
  Stephan
-- 
Stephan Diestelhorst, AMD Operating System Research Center
stephan.diestelhorst at amd.com, Tel.   (AMD: 8-4903)
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