PTLsim Simultaneous Multithreading (SMT)

We're pleased to announce our new Simultaneous Multithreading (SMT) model for full system PTLsim/X.

The SMT model uses the same semantics and cache coherence model as Pentium 4 hyperthreading. Each thread has a separate reorder buffer, load/store queue, fetch queue, branch predictor and related resources, but the functional units, issue queues and caches are shared between threads. The usual x86 locking and ordering semantics are fully implemented, so any application or kernel code that works on a Pentium 4 with hyperthreading should work fine.

Most statistics are recorded separately for each thread in the smtcore.vcpuX data store trees, as well as core-wide totals in the smtcore.total tree.

The SMT core supports up to 16 threads (VCPUs), with all VPUs assigned to a single core with multiple threads. The kernel running inside the virtual machine is still responsible for scheduling and load balancing software threads onto VCPUs (a.k.a. hardware threads), just as in a real machine.

SMT and multi-processor support in general is only available under full system PTLsim/X for obvious reasons. If you're using the userspace only version of PTLsim, only the out of order core (-core ooo) is available.

Note that the existing out of order core does not always work properly with multiple VCPUs, since it lacks the proper locking and cache coherence logic. If you're using multiple VCPUs, always use the SMT core (or the sequential core, which also works with multiple VCPUs) instead.

The SMT code closely follows the structure of the existing OOO core, and is contained in smtcore.cpp, smtpipe.cpp, smtexec.cpp, smtcore.h.

The SMT core must be selected at runtime with the -core smt PTLsim option.

The SMT core presently has the following limitations:

• Up to 16 threads per core. The default limit is 4 threads, but this can be adjusted at compile time. If the target virtual machine was configured with fewer VCPUs than this limit (including the single processor case), it will still work fine (the other VCPUs are simply never brought up).

• All VCPUs are mapped to a single core with multiple threads. Presently it isn't possible to mix and match multiple cores each with multiple threads, although this will be addressed in the near future.

• Only one issue queue is supported. The ICOUNT thread balancing heuristics become significantly more complicated when multiple clusters and issue queues are used, but we're working on solutions to this.

The SMT core is still considered experimental, since we're still tuning the load balancing heuristics to avoid thread starvation and deadlock.

In the future, we plan to make the SMT core the default, and eventually we'll remove the default OOO core model altogether, since a single processor machine is just a special case of a single-threaded SMT core.

We'll be updating the PTLsim User's Guide and Reference with more information about the SMT core in the near future.

The SMT core was designed and implemented by , so please address any questions about it directly to Hui (). Hui is our resident multi-threading expert, so he'll be able to help you with any questions, bug reports or feature requests.

We hope the SMT support is useful to PTLsim users - it has been our most popular feature request. Enjoy!