Contents

• PTLsim User's Guide
  • Introducing PTLsim
    • Introducing PTLsim
    • History
  • Getting Started
    • Documentation Map
    • Additional Resources
  • PTLsim Architecture
  • PTLsim Code Base
    • Code Base Overview
    • Common Libraries and Logic Design APIs
      • General Purpose Macros
      • Super Standard Template Library (SuperSTL)
      • Logic Standard Template Library (LogicSTL)
      • Miscellaneous Code
  • x86 Instructions and Micro-Ops (uops)
    • Micro-Ops (uops) and TransOps
    • Load-Execute-Store Operations
    • Operation Sizes
    • Flags Management and Register Renaming
    • x86-64
    • Unaligned Loads and Stores
    • Repeated String Operations
    • Checks and SkipBlocks
    • Shifts and Rotates
    • SSE Support
    • x87 Floating Point
    • Floating Point Unavailable Exceptions
    • Assists
  • Decoder Architecture and Basic Block Cache
    • Basic Block Cache
    • Identifying Basic Blocks
    • Invalid Translations
    • Self Modifying Code
    • Memory Management of the Basic Block Cache
  • PTLsim Support Subsystems
    • Uop Implementations
    • Configuration Parser
    • Memory Manager
      • Memory Pools
      • Garbage Collection and Reclaim Mechanism
  • Statistics Collection and Analysis
    • PTLsim Statistics Data Store
      • Introduction
      • Node Attributes
      • Configuration Options
    • PTLstats: Statistics Analysis and Graphing Tools
    • Snapshot Selection
    • Working with Statistics Trees: Collection, Averaging and Summing
    • Traversal and Printing Options
    • Table Generation
      • Bargraph Generation
    • Histogram Generation
  • Benchmarking Techniques
    • Trigger Mode and other PTLsim Calls From User Code
    • Notes on Benchmarking Methodology and ``IPC''
    • Simulation Warmup Periods
    • Sequential Mode
  
  
• PTLsim Classic: Userspace Linux Simulation
  • Getting Started with PTLsim
    • Building PTLsim
    • Running PTLsim
    • Configuration Options
    • Logging Options
    • Event Log Ring Buffer
    • Simulation Start Points
    • Simulation Stop Points
    • Statistics Collection
  • PTLsim Classic Internals
    • Low Level Startup and Injection
      • Startup on x86-64
      • Startup on 32-bit x86
    • Simulator Startup
    • Address Space Simulation
    • Debugging Hints
    • Timing Issues
    • External Signals and PTLsim
  
  
• PTLsim/X: Full System SMP/SMT Simulation
  • Background
    • Virtual Machines and Full System Simulation
    • Xen Overview
  • Getting Started with PTLsim/X
    • Building PTLsim/X
    • Running PTLsim
    • Booting Linux under PTLsim
    • Running Simulations: PTLctl
    • PTLsim/X Options
    • Live Updates of Configuration Options
    • Command Scripts
    • Working with Checkpoints
    • The Nature of Time
    • Other Options
  • PTLsim/X Architecture Details
    • Basic PTLsim/X Components
      • Xen Modifications
      • PTLsim Monitor (PTLmon)
    • PTLsim Core
    • Implementation Details
      • Page Translation
      • Exceptions
      • System Calls and Hypercalls
      • Event Channels
      • Privileged Instruction Emulation
    • PTLcalls
    • Event Trace Mode
    • Multiprocessor Support
  
  
• Out of Order Processor Model
  • Introduction
    • Out Of Order Core Features
    • Processor Contexts
    • PTLsim Machine/Core/Thread Class Hierarchy
  • Out Of Order Core Overview
    • Event Log Ring Buffer
  • Fetch Stage
    • Instruction Fetching and the Basic Block Cache
    • Fetch Queue
  • Frontend and Key Structures
    • Resource Allocation
    • Reorder Buffer Entries
      • ROB States
    • Physical Registers
      • Physical Registers
      • Physical Register File
      • Physical Register States
    • Load Store Queue Entries
      • Register Renaming
      • External State
    • Frontend Stages
  • Scheduling, Dispatch and Issue
    • Clustering and Issue Queue Configuration
    • Cluster Selection
    • Issue Queue Structure and Operation
      • Implementation
      • Other Designs
    • Issue
  • Speculation and Recovery
    • Misspeculation Cases
    • Redispatch
      • Redispatch Process
      • Deadlock Recovery
      • Statistical Counters
    • Annulment
      • Branch Mispredictions
      • Annulment Process
  • Load Issue
    • Address Generation
    • Store Queue Check and Store Dependencies
    • Data Extraction
    • Cache Miss Handling
  • Stores
    • Store to Store Forwarding and Merging
    • Split Phase Stores
      • Load Queue Search (Alias Check)
      • Store Queue Search (Merge Check)
  • Forwarding, Wakeup and Writeback
    • Forwarding and the Clustered Bypass Network
    • Writeback
  • Commitment
    • Introduction
    • Atomicity of x86 instructions
    • Commitment
    • Additional Commit Actions for Full System Use
    • Physical Register Recycling Complications
      • Problem Scenarios
      • Reference Counting
      • Hardware Implementation
    • Pipeline Flushes and Barriers
  • Cache Hierarchy
    • General Configurable Parameters
    • Initiating a Cache Miss
    • Filling a Cache Miss
    • Translation Lookaside Buffers
  • Branch Prediction
    • Introduction
    • Conditional Branch Predictor
    • Branch Target Buffer
    • Return Address Stack
  
  
• Appendices
  • PTLsim uop Reference
  • Performance Counters
    • General
    • Summary
    • Simulator
    • Decoder
    • Out of Order Core
    • Cache Subsystem
    • External Events
  
  
• Bibliography