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Introducing PTLsim
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Contents
Contents
PTLsim User's Guide
Subsections
Introducing PTLsim
Introducing PTLsim
History
Getting Started
Documentation Map
Additional Resources
PTLsim Architecture
PTLsim Code Base
Code Base Overview
Common Libraries and Logic Design APIs
General Purpose Macros
Super Standard Template Library (SuperSTL)
Logic Standard Template Library (LogicSTL)
Miscellaneous Code
x86 Instructions and Micro-Ops (uops)
Micro-Ops (uops) and TransOps
Load-Execute-Store Operations
Operation Sizes
Flags Management and Register Renaming
x86-64
Unaligned Loads and Stores
Repeated String Operations
Checks and SkipBlocks
Shifts and Rotates
SSE Support
x87 Floating Point
Floating Point Unavailable Exceptions
Assists
Decoder Architecture and Basic Block Cache
Basic Block Cache
Identifying Basic Blocks
Invalid Translations
Self Modifying Code
Memory Management of the Basic Block Cache
PTLsim Support Subsystems
Uop Implementations
Configuration Parser
Memory Manager
Memory Pools
Garbage Collection and Reclaim Mechanism
Statistics Collection and Analysis
PTLsim Statistics Data Store
Introduction
Node Attributes
Configuration Options
PTLstats: Statistics Analysis and Graphing Tools
Snapshot Selection
Working with Statistics Trees: Collection, Averaging and Summing
Traversal and Printing Options
Table Generation
Bargraph Generation
Histogram Generation
Benchmarking Techniques
Trigger Mode and other PTLsim Calls From User Code
Notes on Benchmarking Methodology and ``IPC''
Simulation Warmup Periods
Sequential Mode
Matt T Yourst 2007-09-26